The DSP picks the modulator

Two bullets, read together

Vendors write product announcements for fast reading, so the interesting ones are worth a slow reading. In March 2026 Broadcom announced the industry’s first 400G-per-lane optical DSP. Two of its product highlights are a few lines apart:

Monolithic 3 nm 1.6T, eight to four, PAM4 DSP with integrated laser driver.

Proven interoperability with Broadcom’s 400G EML and photodiode.

Separately, each line is ordinary. Integration removes one part. Every vendor claims interoperability. Together, the two lines describe a different situation. Think of a module maker that spent five years on a silicon photonics platform and now wants to build a 3.2T module.

The only announced DSP at this lane rate has a driver already inside it. Broadcom qualified that driver against a modulator that the module maker does not make.

Broadcom never says that the part cannot drive a Mach-Zehnder (a modulator that splits the light into two arms and shifts their phase). Its own product brief says the opposite of what the press release implies. The brief states that the line transmitter supports these modulators:

• thin-film lithium niobate modulators
• differential EMLs
• advanced high-bandwidth silicon photonics modulators

It also states that the part supports direct drive to advanced low-Vpi thin-film lithium niobate modulators. Vpi is the half-wave voltage, the voltage that shifts the phase by half a wave.

Read the two documents together, and the qualifier carries the meaning. Direct drive from a driver small enough for a digital die works when the modulator’s half-wave voltage is low. The brief says exactly that: low-Vpi lithium niobate. Silicon’s Mach-Zehnder is the modulator whose half-wave voltage is not low. The sentence does not promise direct drive for it.

The qualification claim is the one that a purchasing decision actually depends on. It names exactly one pairing: Broadcom’s own EML and photodiode. Also, the title of the company’s OFC 2026 paper on the subject names direct-detect EML.

The documents even contradict each other. The press-release bullet says integrated laser driver. But in the family, only this product brief omits the phrase from its title. Its application diagram shows the driver and the laser together in one block outside the chip. Marketing and engineering do not yet agree where the integration boundary of this part is.

This is worth understanding, not only criticizing. The engineering under it is real, and it explains a decision that looks arbitrary from the outside.

A driver is not a generic block

The clearest evidence is not in a DSP datasheet. It is in the catalog of a company that sells discrete drivers for every modulator type. The catalog gives the output topology and swing of each part.

Below 400G per lane, parts sold for electro-absorption modulators are differential in and single ended out at 1.5 to 1.8 volts. Parts sold for silicon Mach-Zehnder modulators are differential out at 3.0 to 3.6. This is not a setting. It is a different output stage for a different load.

An absorption modulator is a small reverse-biased diode. A modest swing across a low impedance is enough to operate it. A Mach-Zehnder is a pair of long phase shifters. It needs volts of differential drive to reach a half-wave shift.

At 448G per lane, the difference between the two driver types is smaller, but it does not disappear. The two parts that launched in March 2026 are both differential:

• The Mach-Zehnder driver operates at 260 gigabaud and 2.5 volts differential.
• The EML driver operates at 224 gigabaud and 2.0.
• Their power per channel is within ten milliwatts of each other.

The EML moved to differential drive, and the amplitudes are now similar. The difference now is in the advertising for each part. The Mach-Zehnder part is sold on bandwidth beyond 120 GHz, gain, output voltage and linearity. The EML part is sold on low power.

One part does both. It is differential, it has a three-volt swing, and its vendor built it to the Mach-Zehnder specification. A part that serves both families must meet the specification of the harder one.

The reason underneath: bandwidth, and who makes it up

The output stage explains why a driver is modulator-specific. It does not explain why the integrated driver went with EML. For that, look at a contribution that Huawei made to the IEEE study group on 400G-per-lane signaling.

Its rule is simple. A lane needs analog bandwidth between 0.45 and 0.55 of its baud rate. If 448 gigabits run as PAM4, the baud rate is 224, so the requirement is 101 to 123 GHz. The available bandwidth of each part is as follows:

• The driver itself: about 130.
• An EML: about 110.
• Thin-film lithium niobate: about 110.
• A silicon Mach-Zehnder: about 70, which the table marks, politely, as slightly low.

Seventy against a hundred and one is a deficit of about 31 GHz. The contribution says plainly how the industry closes it: bandwidth compensation through the modulator driver is available. An external driver with 120 to 130 GHz of bandwidth peaks the modulator’s roll-off. That is, it boosts the top of the band, where the modulator response decreases. It uses some of its gain and linearity to do this.

Now the integrated-driver decision no longer looks arbitrary. To peak a 70 GHz modulator with 130 GHz of analog bandwidth is a demanding analog function. It uses much power and needs a large output stage. This type of function does not fit well next to a 3 nm digital die full of equalizers. Pair the integrated driver with a modulator that already has 110 GHz, and the driver’s job becomes easy enough to put inside.

The DSP vendor did not choose EML because it dislikes silicon. It chose the modulator whose bandwidth let the driver move inside.

Integration is not a direction

A second change inside these parts makes the word integration less simple. Both leading vendors made this change in the same generation.

At 100G per lane, the flagship devices integrated the TIA as well as the driver. Broadcom gives its 100G-per-lane part this full title: an 800G transceiver PHY with integrated TIA and laser driver. Marvell announced its equivalent as the industry’s first 5 nanometer PAM4 DSP to integrate both a transimpedance amplifier and a linear driver. Two vendors, same claim, same generation.

Now look at the 200G-per-lane parts from the same two companies. Every one of them integrates the driver. Not one integrates the TIA. Marvell’s portfolio page gives this as a specification, not as an omission: integrated 56 or 112 gigabaud laser drivers, integrated 56 gigabaud TIA. Marvell integrates the TIA only at the older baud rate. Broadcom’s application diagrams show the photodiode and TIA outside the die.

Marvell published the reason, and it is mechanical, not electrical. At 100G per lane, a wire bond can connect a TIA inside the module. At 200G per lane, the parasitics of the bond wire degrade the signal. The design therefore flips the photodiode and mounts it directly onto the input pads of the TIA. If the TIA must sit on the photodiode, it cannot also be on the digital die a centimeter away.

So the same generation that moved the driver into the DSP moved the TIA out of it. Integration does not move in one direction over time. Each integration decision is local, and the tightest physical constraint at that moment decides it. The driver moved in because a low half-wave voltage made it possible. The TIA moved out because a bond wire stopped working.

The census, and the loudest silence

Now count the vendors. At 200G per lane there are many:

• Broadcom’s Sian family.
• Marvell’s Nova and Ara.
• Acacia’s Kibo.
• Credo’s Cardinal.
• MaxLinear’s Rushmore.
• The line that Qualcomm acquired with Alphawave and renamed Dragonfly. Qualcomm lists its 200G optical part as the Dragonfly O200.

That is six vendors and several generations. For the newest parts, a 3 nm node is now the minimum.

At 400G per lane there is one part, and it is sampling.

The most informative absence is Marvell’s. In March 2025 Marvell demonstrated the industry’s first complete 400G-per-lane electrical-to-optical link at 224 gigabaud. It used discrete parts: a DSP, TIAs and modulator drivers as separate silicon. A year later, at OFC 2026, it launched four new optical DSPs. Three are PAM4 parts at 200G per lane. The fourth, Aquila M, is a coherent-lite part. None is a 400G-per-lane PAM4 DSP. Marvell proved the lane rate first, but it shipped the generation below it.

The field, and the bar it has to clear

Two views of the same generation change. One counts the parts you can actually buy at each lane rate; the other puts the analog bandwidth each modulator has against what the lane demands.

View

The partsThe bandwidth bar

Per-lane rate

100G200G400G

1

announced part at 400G per lane

1

vendor

• Broadcom Taurus BCM836403 nm · 2026-03-11

  EML driver integratedgearboxretimed

  The only announced 400G-per-lane optical DSP. An 8:4 gearbox with an integrated laser driver, described as interoperating with Broadcom 400G EMLs and photodiodes. Mass production expected late 2026.

One part, sampling. The vendor that demonstrated this lane rate first, a year earlier and with discrete drivers, shipped an all-200G portfolio instead.

Parts, nodes and driver wording are taken from vendor releases and product pages; a driver is listed as committing to a modulator family only where the vendor names one. Device bandwidths and the 0.45 to 0.55 rule come from a Huawei contribution to the IEEE 802.3 study group on 400 Gbps per lane signaling, May 2026. Silicon's figure is the one that table marks as slightly low for PAM4.

Count the same field by supplier geography, and it becomes smaller again. Every merchant 200G-per-lane optical DSP belongs to a Western company. A merchant part is one that any module maker can buy.

This is not an inference from silence. The largest optical module maker in the world states it in its own filings. For electrical chips at 200G and above, the filing says, the suppliers are mainly overseas. At 100G and below, domestic suppliers already have mass-production capability. The domestic design houses that exist are one or two generations back.

That concentration needs a separate essay, but it makes this argument stronger. Suppose an integrated driver picks the modulator, and the DSP with that driver comes from one of six companies. Then a very small group of companies makes a choice that looks like the module maker’s. The architectures that skip the DSP are then a sourcing strategy as much as a power strategy.

Two vendors make any simple story less simple, and that is the useful part. Credo’s Cardinal family, at 200G per lane, advertises integrated high-swing laser drivers for both EML and silicon photonics. Credo’s annual filing uses these words: multiple integrated laser-driver options for silicon photonics, EML and VCSEL-based designs.

Broadcom makes the same point more clearly: it sells the same silicon twice, and the product title says so. The BCM85821 is a five-nanometer 800G PAM-4 transceiver PHY. The BCM85822 is a five-nanometer 800G PAM-4 transceiver PHY with an integrated laser driver. The two descriptions are identical except for one clause. So the module maker does not decide whether a module has a discrete driver socket. Whoever chose the part number made that decision earlier in the supply chain.

So one driver can serve both families, at a cost: an output stage built to the harder of the two specifications. Three volts is the Mach-Zehnder requirement, not the EML one. The EML uses less of that output stage. But the larger stage costs die area and power on every module, including modules that did not need it. At 200G per lane, the bandwidth requirement is half as demanding, and that trade is affordable. Nobody yet showed that it is affordable at 400.

What could change the answer, and probably will

Three developments are worth watching, and none of them supports a settled conclusion.

The first is that silicon already reached the lane rate. Twelve days after the Taurus announcement, Tower Semiconductor and Coherent demonstrated 400 Gbps per lane. They used a silicon Mach-Zehnder built in a production silicon photonics process. A commercial silicon-germanium part drove it, and the eye was clearly open at 420. Coherent showed both routes at the same conference, an EML and a silicon PIC (photonic integrated circuit). It labeled both as capability statements, not products.

So the question at 400G per lane is not whether silicon works. The question is how much driver complexity it costs to make silicon work.

The second is modulation. Suppose 448 gigabits moves from PAM4 to PAM6 (six signal levels). Then three numbers change:

• The baud rate decreases from 224 to 173.
• The bandwidth requirement decreases to about 78 GHz.
• Silicon’s deficit decreases from 31 GHz to about 8, which a driver can plausibly peak.

This is not idle speculation. The OIF launched its two 448G electrical projects in February 2026. As of March, its loss budgets, modulation and jitter targets were still undefined. PAM4, PAM6 and PAM8 are all still possible, and the channel is the reason. The modulation choice at 448G is, among other things, a decision about which modulators are viable.

The third is that the standard is years behind the silicon. The IEEE approved the project for 400G-per-lane signaling, P802.3dv, in September 2026. Its draft plan expects to finish in September 2029. It does not define a 3.2T Ethernet rate at all. The industry uses this lane rate to make existing rates denser, not to create a new one. Silicon shipped three years before the document that will describe it.

The pressure from the other direction

The DSP decides which modulator a module uses. At the same time, a quieter argument asks whether the module needs a full DSP at all. Linear pluggable optics have no DSP in the module. Arista told the SEC that its 1.6T platforms support linear pluggable optics and cut interconnect power by approximately 60 percent. Cisco puts the saving at 50 percent per module and 30 percent for the system on its 800G platform.

The practitioner view at ECOC 2025 was blunt. It made three points:

• Linear pluggable optics were a triumph of wishful thinking over mathematics.
• Deployment remains small.
• At 200G per lane they are unusable, and attention is moving to half-retimed optics instead.

How much is the DSP actually worth in watts? Three sources answer this question, and they agree. That is unusual enough to state plainly:

• A component vendor that sells the analog alternative publishes the full ladder at 200G per lane. Fully retimed modules are at 23 to 25 watts today and about 20 with the next DSP generation. Half-retimed modules are at roughly 16, and linear pluggable modules target about 10.
• A system vendor ships the same 1.6T module in two versions and publishes both. The fully retimed version is 24 watts typical. The transmit-only retimed version is 17.
• A contract manufacturer on a different photonics platform shows an even larger gap. It quotes a fully retimed 1.6T module under 26 watts typical. Its half-retimed version is 11, built to the OIF’s retimed-transmitter, linear-receiver agreement.

In round numbers, if you remove the receive half of the DSP, you save something like a quarter to a third of module power. If you remove all of it, you save more than half. That is the benefit, and it explains why nobody defends the full DSP as a principle.

The same component vendor also publishes the cost. Linear pluggable optics currently target about 22 decibels of die-to-die loss, and possibly 26 later. A retimed module divides that path at its DSP, and each half gets its own budget. Without the DSP, the switch’s own electrical transmitter must cover the full path from switch die to module die. That limit is the cost of the saving.

The DSP vendors do not oppose this change. They sell products for it:

• Marvell shipped a transmit-only part in 2024 and a transmit-retimed 200G-per-lane part in 2026.
• Acacia’s 1.6T DSP can bypass its receive-side processing and keep its diagnostics.
• Credo built a dedicated transmit-only device for linear receive.

The half-retimed architecture changes a threat to unit volume into pressure on price. That is a much better problem for a chip vendor to have.

At 400G per lane, the balance moves back toward the DSP. Huawei’s feasibility study on co-packaged optics (optics in the same package as the switch) reaches two conclusions. Above 15 decibels of electrical link loss, strong transmit peaking and receive-side maximum-likelihood sequence estimation are mandatory. It puts realistic co-packaged loss at 15 to 20 decibels. The generation that makes linear drive attractive on power is the same generation that makes the receiver’s arithmetic hard to skip.

What to take away

1. Read the interoperability bullet, not the headline rate. Read the brief, not the release. Claimed support is a wide list. Proven interoperability is one pairing, and the brief promises direct drive only where the half-wave voltage is low.
2. Drivers differ by modulator because their output stages differ. Below 400G per lane, EML drivers are single ended at 1.5 to 1.8 volts. Silicon Mach-Zehnder drivers are differential at 3.0 to 3.6. Dual-capable parts exist, and they meet the harder specification.
3. The bandwidth arithmetic explains the difference. 448G PAM4 needs 101 to 123 GHz. EML and thin-film lithium niobate have 110, and silicon has about 70. An external 130 GHz driver closes that gap.
4. The ecosystem decreases from six vendors at 200G per lane to one announced part at 400, and all of them are Western. The most informative absence belongs to the vendor that demonstrated the lane rate first.
5. Three developments could change this picture. Silicon reached 420 Gbps in a production process, so that one already happened. A move to PAM6 is still undecided. The standard is not due until 2029.

The general habit is worth more than the specific answer. When a component integrates a neighbor, the integration is a bet on what that neighbor will be:

• A DSP that integrates the driver bets on a modulator.
• A switch that integrates the retimer bets on a link budget.
• A package that integrates the optics bets on a laser.

Each bet saves power and cost today. It also limits what the buyer can choose tomorrow. The announcement will always describe the first half and not mention the second.