Photonic ICs for AI optical interconnect.
We make photonic chips that turn 200G and 400G lanes into light.
One platform, five parts
1.6T DR8 and 800G FR4 transmit chips are available now, built to the IEEE 802.3dj port definitions at 200G per lane. DR8 and FR8 receivers and a 6.4T near-package transceiver, built to the Open CPX MSA, are in development. All of it runs on a mature CMOS process with Mach-Zehnder modulation.
Available now
- DR8 TX chipDR8
- FR4 TX chipFR4
In development
- DR8 RX chipDR8
- FR8 RX chipFR8
- 6.4T NPO TRx chipOpen CPX MSA
Where our chip sits
Open a pluggable module and most of what you find serves one chip. The switch sends electrical lanes in at the back, and light leaves through the fiber at the front. The photonic IC is where one becomes the other, and it is the part we make. The module around it is the module maker's design. The package changes from one form factor to the next, and the job of the photonic IC does not.
The air-cooled pluggable that carries most 800G and 1.6T optics today. Select a part, on the drawing or in this list, to see what it does. Schematic: it shows where things sit, not how any particular module is built.
The metal shell is both the enclosure and the heat sink. On an OSFP module the fins are part of the top shell. They run front to back, in line with the air that the switch pulls through the cage.
A soft, conductive pad that closes the gap between the hottest chips and the lid. Their heat then goes to the fins instead of staying in the board.
Takes the electrical lanes from the switch, undoes what the board trace did to them, retimes them and drives the optics. It is the largest single consumer of power in most modules, which is why linear-drive designs try to remove it.
Silicon does not emit light efficiently. A continuous-wave laser supplies light from outside the chip, and the photonic IC writes the data onto it.
Modulators turn each electrical lane into a stream of light, and photodetectors turn received light back into lanes. This is the part we make: photonic chips for 200G and 400G per lane.
A small microcontroller that watches temperatures, laser bias and optical power. It answers the switch’s management queries through the CMIS memory map.
Fibers attach at the edge of the photonic IC. They run to the optical connector at the front of the module, where the cable plugs in.
Carries everything above. The gold fingers at the back plug into the switch’s cage, and every electrical lane between the switch and the optics crosses that edge.
A liquid-cooled pluggable from the XPO MSA, which Arista announced in March 2026. Two paddle cards sit back to back around a cold plate, so one module carries far more lanes than an OSFP. Schematic, not to scale: the MSA defines the interfaces, not the layout of the chips.
A plain metal shell with no fins. Liquid removes the heat, so the shell only has to enclose the module. The pull tab at the front releases it from the cage.
A cold plate sits between the two paddle cards and takes heat from the chips on both. Coolant enters and leaves through two ports at the back of the module. Air across a faceplate cannot remove the heat of a module this dense.
Takes the electrical lanes from the switch, undoes what the board trace did to them, retimes them and drives the optics. It is the largest single consumer of power in most modules, which is why linear-drive designs try to remove it.
Silicon does not emit light efficiently. A continuous-wave laser supplies light from outside the chip, and the photonic IC writes the data onto it.
Modulators turn each electrical lane into a stream of light, and photodetectors turn received light back into lanes. This is the part we make: photonic chips for 200G and 400G per lane.
A small microcontroller that watches temperatures, laser bias and optical power. It answers the switch’s management queries through the CMIS memory map.
Fibers attach at the edge of the photonic IC. They run to the optical connector at the front of the module, where the cable plugs in.
Two circuit cards instead of one, mounted back to back. Each card has its own gold fingers at the back, so the module presents two rows of electrical lanes to the switch.
A new pluggable form factor from NVIDIA and Cisco, announced at the OCP Global Summit in October 2026. It keeps a package close to OSFP size and carries more lanes, each at 400G. No internal layout is public yet, so this drawing reuses the OSFP anatomy with more fibers.
The shell and its heat sink. The announcement describes air cooling and hybrid cooling, and the mechanical drawings are not public yet. The drawing keeps the OSFP fins for that reason.
A soft, conductive pad that closes the gap between the hottest chips and the lid. Their heat then goes to the fins instead of staying in the board.
Takes the electrical lanes from the switch, undoes what the board trace did to them, retimes them and drives the optics. It is the largest single consumer of power in most modules, which is why linear-drive designs try to remove it.
Silicon does not emit light efficiently. A continuous-wave laser supplies light from outside the chip, and the photonic IC writes the data onto it.
Modulators turn each electrical lane into a stream of light, and photodetectors turn received light back into lanes. This is the part we make: photonic chips for 200G and 400G per lane.
A small microcontroller that watches temperatures, laser bias and optical power. It answers the switch’s management queries through the CMIS memory map.
More lanes in the same size of package means more fibers through the same front connector. That density is the point of the form factor.
Carries everything above. The gold fingers at the back plug into the switch’s cage, and every electrical lane between the switch and the optics crosses that edge.
Near-package optics. The optical engine leaves the front panel and plugs into a socket on the switch board, beside the switch chip. The Open CPX MSA standardizes that socket and leaves the inside of the engine to its maker. Schematic: the drawing does not choose an engine design.
The engine shares the cooling of the board around the switch chip. Depending on the system, that is a heat sink or a cold plate.
Drivers for the modulators and amplifiers for the photodetectors. Some engines add a DSP, and many leave the retiming to the switch chip. Open CPX leaves that choice to the engine maker.
Silicon does not emit light efficiently, so a continuous-wave laser supplies it. Open CPX allows the laser inside the engine or in a separate external laser module. The drawing puts it inside only for simplicity.
Modulators turn each electrical lane into a stream of light, and photodetectors turn received light back into lanes. This is the part we make: photonic chips for 200G and 400G per lane.
Fibers leave the engine and run across the board to the front panel, where the cables connect.
The small board that carries the engine’s chips and plugs into the socket.
The part that Open CPX standardizes: the connector, its footprint and how the engine seats. A failed engine comes out of its socket, and the switch board stays as it is.
The switch chip in its package. Near-package optics shortens the electrical path from this chip to the optics, from the width of the board to a few centimeters.
The switch’s own board. The electrical lanes from the switch chip run a short trace to the socket instead of across the board to a cage.
Compute with electrons.
Connect with light.
Where the optics sit
Each generation, the optics moves closer to the switch ASIC, because the electrical channel between them is the limit. Our current parts serve the first two placements. Co-packaged optics is where the handoff moves next.
- 01Front panelCurrent parts
Pluggable optics
Modules in the front-panel cage, built to multi-source agreements. Swap one in the field without opening a chassis. The price is an electrical channel that runs the whole width of the board.
- 02On boardCurrent parts
Near-package optics (NPO)
The optical engine moves onto the line card beside the ASIC, cutting the electrical channel to centimeters. Most of the benefit of co-packaging, without entering the package.
- 03In packageDirection
Co-packaged optics (CPO)
The engine shares the ASIC package itself: millimeters of electrical reach, and the tightest thermal and assembly constraints in exchange.
From the Insights
All articlesWorking notes on the parts of AI infrastructure that are hard to get a straight answer on. Every figure has a cited source.