The test menu is public. The results are not.

A swap that no longer exists

A technician walks to a switch with a failed link. The technician pulls the pluggable module out of the front panel, pushes a new one in, and the link comes back. The whole repair takes less time than reading the ticket. That swap set how the industry thought about optical reliability. A module that failed was a spare part, not an outage.

Co-packaged optics (CPO) removes the swap. In CPO, the optical engine sits in the same package as the switch chip. Cisco’s engineers put the consequence in one sentence: a failed optical engine is no longer a simple swap, so its reliability must be engineered and qualified like semiconductor silicon. Meta makes the same point from the operator side. A co-packaged failure can mean a chassis replacement, not a module replacement.

That change in the cost of a failure is the reason for a new standard. The question this essay asks is narrower. The standard now says what to test. Who tested, and what did they find?

Who owned reliability before

Optical qualification grew up at the module level. Telcordia GR-468, first issued in 1998 and revised in 2004, is the reference most module vendors cite. It sets a menu of stress tests for a finished optoelectronic device: operating life, storage, damp heat and temperature cycling, run on samples of the final product.

Silicon photonics breaks that model in two places. First, the photonic die is a semiconductor chip made in a foundry. The foundry qualifies its process at the wafer level, as it does for any CMOS process. Second, between the wafer and the module there are several levels that no document governed:

• The micro-optic components on the die, such as modulators, photodiodes and heaters.
• The bare die with all components working together.
• The laser, attached to or grown on the photonic die.
• The assembled chipset, the photonic die together with its electrical chips.
• 2.5D and 3D stacks, built with through-silicon vias or chip-on-chip bonding.

Each customer and supplier negotiated these levels program by program. Cisco says so directly in its deck. A foundry engineer from Advanced Micro Foundry wrote the same in 2023: no reliability standard existed for laser structures coupled to a photonic circuit. The co-packaging documents did not fill the gap either. OIF’s 3.2T co-packaged module agreement marks its durability rows “to be determined”.

What JESD264 changes

A task group under JEDEC committee JC-14.3 wrote JESD264, and Cisco led the task group. The group existed by 2020, when CompoundTek announced that it joined. JEDEC published the standard on 1 October 2026. The draft that Cisco presented in July has thirteen sections, from general requirements to ongoing reliability testing.

Its central idea is to qualify the platform once. A foundry or a design house qualifies the building blocks of its process design kit (PDK, the library of qualified devices a designer uses), then the bare die, then an assembled chipset. After that, later products on the same qualified PDK do not requalify the chipset. Only the standard module-level qualification remains. Qualification by similarity and delta qualification are also allowed, with a documented comparison against a reference device.

The stress conditions come from silicon, not from optics. The draft points to JESD47, the JEDEC qualification standard for integrated circuits:

• High temperature operating life at 85, 125 or 175 °C, for 2000 hours.
• High temperature storage at 150 or 175 °C, for 2000 hours.
• Temperature and humidity with bias at 85 °C and 85 percent humidity, for 1000 hours.
• Temperature cycling from -40 to 125 °C, for 500 cycles.

Those temperatures are higher than most optical tests use. That is the point: the photonic die will sit next to a hot switch chip, so it gets silicon conditions.

Three things are outside the scope. Production test and burn-in stay with each manufacturer. Lasers in their own package, such as a separate transmitter subassembly, keep their existing procedures. The finished module stays with GR-468 and its companions. JESD264 covers what sits between the wafer and the module, which is exactly the part that had no owner.

What a passing result can prove

A qualification standard sets sample sizes, and sample sizes set what a pass can prove. The arithmetic is short, and it is worth doing before reading any qualification report.

When n parts pass a test with zero failures, the failure fraction is below 1 - (1 - C)^(1/n) with confidence C. For the JEDEC silicon plan of three lots of 77 parts, n is 231. At 90 percent confidence, the bound is about 1 percent. So a clean operating-life result on 231 parts shows that fewer than about 1 in 100 parts fail within the test. It does not show 1 in 10,000.

The draft asks for much more on wire bonds and attached components: less than 0.01 percent failure at 90 percent confidence. The same formula says that target needs about 23,000 passing samples. The test uses 30 dies per interval, so each die must contribute more than 700 bonds to reach that count. This is why the draft says to pull every wire and shear every ball. The statistic counts bonds, not dies.

Lifetime is the harder part. Nobody tests for fifteen years. A test runs for 2000 hours at high temperature, and an acceleration model converts that to years at the use temperature. For accelerated life tests, the draft lets the supplier provide the end-of-life criteria and the acceleration model. That is reasonable, because activation energy depends on the failure mechanism. But it means two suppliers can pass the same test and claim different lifetimes. A buyer must ask for the model and its source, not only the pass.

Following the wafers

A standard only matters where there is volume to qualify. One practical test for volume capability is to follow shipping products back to the fab that made the photonic die. Public sources support the following picture as of October 2026.

The table sorts itself into three groups:

1. Named products in volume. Tower and Intel. Intel’s fab serves only Intel’s own products, so Tower is the only merchant foundry with named high-volume transceiver customers in public.
2. Volume without names. GlobalFoundries reports real revenue, and STMicroelectronics reports high-volume production, but neither names the transceiver customers.
3. Starting now. TSMC has the most important named sockets in co-packaging, but its volume began in 2026. UMC delivered its first production wafers in July 2026.

The last column is the finding. Across seven foundries, one platform has quantified qualification results in public, and a design company published them, not the foundry. The others may hold excellent data. They do not publish it. Before JESD264, there was no common menu to publish against. That excuse now ends.

What the data looks like at the top

Operators measure reliability differently. They count device-hours in the field and divide by failures. The OIF co-packaging framework sets the targets in failures in time (FIT, failures per billion device-hours):

• 300 FIT for today’s pluggable modules.
• 10 FIT for a 3.2T co-packaged engine.
• 50 FIT for its laser source.

The same zero-failure arithmetic applies to hours. To show a rate below 300 FIT at 90 percent confidence takes about 7.7 million device-hours. To show 10 FIT takes about 230 million.

Meta runs the largest public co-packaged test. At ECOC 2025, Meta and Broadcom reported about five times better reliability than a pluggable control group, with the failures tied to the remote laser source. Broadcom cited one million cumulative 400G-equivalent port device-hours without a link flap. By March 2026, Meta reported more than 50 million device-hours on its phase 2 systems. PhotonCap reports a Meta and Broadcom paper at OFC 2026 at 36 million hours. The counts differ by date and venue, and Meta’s “device” need not equal one engine.

Even at 50 million hours, the count is below a quarter of what the 10 FIT target needs. Meta said so itself: there are too few failures to set a confident mean time between failures. Test hours on the scale of the pluggable target are now routine. Test hours on the scale of the co-packaged target are not yet published by anyone.

What to take away

JESD264 is a real step. It gives the industry one vocabulary for the levels between wafer and module, and it puts the photonic die on silicon test conditions because co-packaging puts it in silicon’s environment.

But the standard is the test menu. The results are still private. For a buyer, three questions now have a standard form:

1. Which JESD264 sections did the platform pass, on how many lots?
2. Which acceleration model and activation energy convert the hours to years, and where do they come from?
3. Is the platform the one that ships in volume, or a different process at the same foundry?

A fourth question comes from the standard’s first clause: which configuration does the result cover? A companion essay follows that clause and its four requalification triggers.

The wider lesson applies to any young technology that borrows an old reliability language. A shared menu makes results comparable. It does not make them exist. In silicon photonics, the first platforms to publish JESD264 results in full will show which foundries are ready for co-packaging, sooner than any capacity announcement.