The wafer under the wafer

The smallest line on a shrinking income statement

If you read Soitec’s fiscal 2026 results with no context, the company looks like a casualty of the smartphone cycle. Revenue fell 34 percent to €592 million. The year included €105 million of impairments, with a €29 million write-off on an unfinished fab extension in Singapore. The operating line changed to a €131 million loss. On the next call, for the first quarter of fiscal 2027, management put fab loading at 48 percent. Half the machines are idle.

But inside that income statement, one small line had the opposite year. Photonics-SOI is the specialty silicon-on-insulator (SOI) substrate under silicon photonics chips. It passed $100 million of revenue in FY26, “earlier than anticipated,” and doubled again year over year in the first quarter of FY27. Its guidance for the full year is more than double. While the rest of the company waits for the handset cycle to end, its smallest product is now the wafer under the AI optics trade.

Each of the tens of millions of silicon photonics modules that the industry now builds each year starts as one of these substrates. This raises a question that the company pointedly does not answer: how many wafers is that? Soitec discloses the revenue but not the volume. But you can count the volume from outside. It is worth counting carefully, because the answer decides where this supply chain can actually break.

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The die grid on a processed wafer. Under every reticle of it sits the substrate this essay counts.

Counting a market nobody discloses

The direct method is one division: revenue divided by price. The revenue side is firm. The company states a floor of $100 million for FY26 and above $200 million for FY27. The price is not public, so this essay gives it an honest bracket instead of a quiet assumption.

The floor of the bracket comes from physics. A photonics-SOI wafer is special because of its buried oxide: 2 to 3 µm of thermal oxide, where an FD-SOI wafer has tens of nanometers. Thermal oxide grows more slowly as it gets thicker. So an oxide two orders of magnitude thicker needs much more than two orders of magnitude more furnace time. The top silicon must also hold optical-grade thickness uniformity. So this wafer cannot have the price of standard SOI, and $1,500 is a defensible lower bound.

The ceiling comes from economics. This wafer is still a Smart Cut product made on existing lines, not an exotic crystal. A peer-reviewed cost curve for open-access silicon photonics puts a fully processed 200 mm wafer near $11,600 at ten-thousand-chip volume. So the bare substrate plausibly stays under $4,000. Divide, and FY26’s $100 million becomes 25,000 to 67,000 wafers. The FY27 guide becomes 50,000 to 133,000.

A division with an assumed denominator needs an independent check, and it is hard to find one that is truly independent. The obvious candidate fails. QY Research counted about 63,700 8-inch-equivalent foundry starts in calendar 2025. That is roughly 28,000 in 300 mm terms. This is just above the FY26 census floor, exactly where a fiscal year that overlaps 2025 should be.

For months, this looked like corroboration. It is not. The same publisher prices a processed wafer at $7,620 and puts the 2025 market at about $485 million. And 63,700 times $7,620 is $485 million. So the count and the price are one estimate in two forms.

The circularity also reaches into this essay. The paragraph above originally used that same price to set its own ceiling. A check that comes from the assumption it tests is not a check. Two scale checks then end the matter:

• Tower alone contracted $1.3 billion of 2027 silicon photonics revenue. That publisher’s implied industry-wide figure for the same year is roughly $848 million.
• The plan for TSMC’s PIC line by itself is to run 6.4 times their entire 2025 industry.

The check that remains shares no data with Soitec’s revenue or with any wafer price. The module-market essay put 2026 silicon photonics module builds around 30 million. Apply three inputs to that number:

• One to two dies per module.
• Shipping-class die areas: 52.5 mm² for a current 800G PIC, and larger for the next generation.
• Photonic yields in PhotonDelta’s 30-to-70-percent band.

The result is on the order of 100,000 300 mm wafers, inside the FY27 band. One independent check agrees. The census holds, but on thinner evidence than it first seemed to have. Photonics-SOI is a tens-of-thousands-of-wafers market this fiscal year, and it moves toward 100,000. The entire AI optics build-out currently depends on it.

The substrate census

Soitec discloses photonics-SOI revenue but not volumes, so the census is revenue divided by an assumed price. Drag the price across its plausible bracket and watch the wafer count against the independent anchors.

Revenue year

FY26 ($100M+)FY27 guide ($200M+)Custom

Photonics-SOI revenue

$100M

Price per wafer (assumption)

$2,500

Wafers per year

40k

treated as 300 mm

Per month

3,333

Of one Singapore-class fab

4%

a ~1M-wafer/yr site

Months of TSMC exit-2026 plan

2.7

at 15k wafers/month

Good PICs implied

18M

80 mm² die, 60% yield

• This censusrevenue ÷ assumed price40k
• Foundry starts, 2025QY Research, converted28k
• PIC demand, 2026our estimate, 30M modules101k
• TSMC capacity plan, exit 2026estimate via TrendForce180k

All bars in 300 mm wafers per year. Revenue floors are Soitec's own ("slightly above $100M" in FY26; FY27 guided to more than double). The price is an assumption bracketed in the essay: at least $1,500 for a 2-3 µm buried oxide, under $4,000 for a Smart Cut product on existing lines, and well below the ~$11,600 a fully processed 200 mm wafer costs on a published open-access cost curve (Rahim et al., 2018). The TSMC source does not state the wafer diameter, and the bar assumes 300 mm. Foundry starts convert QY Research's 63.7k 8-inch equivalents; PIC demand assumes 30M silicon photonics modules at 1.5 dies of 80 mm² each, 60% yield.

The constraint is not the fab

Here, the usual story about this supply chain gets the proportions wrong. A single-source specialty wafer sounds like a capacity limit. The usual reflex is to ask how fast the fabs can grow. But compare the census with the installed base. Soitec’s Singapore site alone is a roughly million-wafer-class fab by design. In 2022 the company started construction of an extension to double it toward two million.

The whole photonics census is a few percent of one such site in FY26. At the top of the FY27 band, it is about a tenth. Other facts point the same way:

• Group fab loading is 48 percent.
• The Singapore extension stayed unfinished long enough that part of it became a write-off.
• An analyst asked directly about constraints, and the CEO’s answer was flat: “no bottleneck at this stage… it’s more lead time to peak than a bottleneck to peak.”

So the fab is wide and half empty. The narrow part is the entry into each customer’s line. A foundry does not change its substrate with a purchase order, as it would for a commodity. Each photonics line qualifies its substrate source into its own process. This qualification is a multi-quarter series of test wafers, process corners and reliability lots. It runs per customer and largely in series.

Soitec’s Singapore fab received qualification for high-volume photonics manufacturing only this past quarter, with its first customers. The company described more qualifications as work in progress. It also reported more than ten photonics customers on multi-year reservation agreements. Capital widens fabs quickly. Qualification widens only at the speed of each party’s test calendar, and money does not make it much faster.

The concentration makes the gate more important. It is worth stating precisely, because the loose version of this claim is wrong. Soitec does not say it is the only supplier. Its own registration document names Shin-Etsu Handotai and GlobalWafers as competitors in Photonics-SOI, and puts no market share on the page. The other companies look like this:

• Shin-Etsu holds a Smart Cut license that dates from the 1990s, but it publishes no photonics-SOI volumes.
• Okmetic does market a photonics SOI product, explicitly for photonic integrated circuits and transceivers. But it is at 150 and 200 mm, with a device layer of a micrometer and up. That is thick-SOI photonics, not the 220-nanometer datacom platform.
• GlobalWafers was the one licensee that fought to stay. It lost its license by termination in 2023 and settled in 2025.

So the defensible claim is narrower than “one supplier,” and more useful. No other company documents a qualified 300 mm photonics-SOI line that ships into a production silicon photonics process. The nearest hard number is in a filing, and it belongs to a customer, not to Soitec.

GlobalFoundries (GF) tells its investors three things:

• A single supplier accounted for about 71 percent of its SOI wafer purchases.
• Replacing that supplier would take an extended period.
• GF is developing alternates, but it does not expect meaningful volume from them soon, and it has no assurance that it ever will.

That figure covers all of GF’s SOI, not the photonics slice. So it gives the size of the dependency, not of the photonics market. It is still the only audited number that anyone published on this question.

This brings the argument back to the gate, not to the supplier list. Several companies can make a photonics substrate. What is scarce is a substrate that a production line already qualified. The calendar causes that scarcity, not the chemistry.

The number that refuses to fit

One public number does not fit this simple picture, and it is better to examine it than to ignore it. Institutional estimates that TrendForce relays put TSMC’s PIC line at 15,000 wafers a month by the end of 2026. The source does not state the wafer diameter. If those are 300 mm wafers, as this essay assumes, that is 180,000 wafers a year for one manufacturer. This is more than the top of the FY27 census for the entire market. As wafer starts, both numbers cannot be true at the same time.

The contradiction can resolve in three ways, and each one predicts a different future:

• The TSMC figure counts capacity under installation, not wafer starts. The module-market essay had to make the same distinction one level up. In this case nothing is wrong. Fabs build ahead of demand, and the census stays true for starts.
• TSMC intends to run anywhere near that plan. Then either Soitec’s photonics revenue is about to grow far faster than “more than double,” or a second substrate source is quietly in qualification. A Shin-Etsu-class announcement is the signal to watch for.
• Neither of these happens. Then the estimate itself was too high. This happened before to capacity numbers that passed through supply chains.

Watch Soitec’s FY28 guidance. Watch for any substrate qualification news from the large wafer houses. Watch whether TrendForce revises its estimate. One of the three must move within about a year, and the one that moves tells you how tight this layer really is.

What to take away

1. Photonics-SOI is a tens-of-thousands-of-wafers market under a hundred-million-unit module industry. $100M+ of FY26 revenue at $1,500 to $4,000 a wafer is 25k to 67k wafers, and the FY27 guide doubles that.
2. The census survives the one check that is truly independent, a 2026 PIC demand estimate near 100k wafers. The other candidate is a published 2025 foundry-start count. It is that publisher’s own market size divided by its own wafer price, so it corroborates nothing.
3. Soitec does not claim to be alone, and names two competitors in its own filing. What no one else documents is a qualified 300 mm photonics line. The one audited number on the dependency is a customer’s. A single supplier accounted for about 71 percent of GlobalFoundries’ SOI purchases, and that covers all SOI, not photonics alone.
4. Capacity is not the constraint. The photonics slice is a few percent of one half-loaded fab in FY26, and about a tenth at the top of the FY27 band. The CEO says there is no bottleneck, only lead time.
5. The real gates are structural: one volume-qualified supplier, and a serial, multi-quarter qualification queue between it and every foundry.
6. The open contradiction is TSMC’s reported PIC plan of 180k wafers a year against a census below 135k. Three outcomes are possible: capacity versus starts, a second source, or a bad estimate. One of them resolves within a year, and it is the single most informative thing to watch in this layer.

The wider habit behind this essay is to read bills of materials vertically. A market always has a most-watched layer, and the shortage is rarely there, because people fix the layer that they watch.

In 2024 the watched layer was lasers. Then silicon photonics cut the laser count from eight per module to two. By that time, the pressure had already moved down into wafers and the substrate under them. There, one company and a queue of qualification calendars now set the pace. Whatever layer everyone watches when you read this, the useful question is the same. What does that layer stand on, and how many of those does anyone actually make?